Semiconductor device and method of fabricating same

ABSTRACT

There are disclosed TFTs having improved reliability. An interlayer dielectric film forming the TFTs is made of a silicon nitride film. Other interlayer dielectric films are also made of silicon nitride. The stresses inside the silicon nitride films forming these interlayer dielectric films are set between −5×10 9  and 5×10 9  dyn/cm 2 . This can suppress peeling of the interlayer dielectric films and difficulties in forming contact holes. Furthermore, release of hydrogen from the active layer can be suppressed. In this way, highly reliable TFTs can be obtained.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. application Ser. No.11/293,111, filed Dec. 5, 2005, now U.S. Pat. No. 7,838,968, which is adivisional of U.S. application Ser. No. 08/835,729, filed Apr. 11, 1997,now U.S. Pat. No. 7,019,385, which claims the benefit of a foreignpriority application filed in Japan as Serial No. 08-115672 on Apr. 12,1996, all of which are incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a thin-film transistor construction andto a method of fabricating it.

2. Description of the Related Art

Thin-film transistors (TFTs) fabricated on a glass substrate or on aninsulating surface have been known. TFTs of this type have beendeveloped especially for use in active matrix liquid crystal displays.

In an active matrix liquid crystal display, millions of pixel electrodesare arranged in rows and columns, and TFTs are connected with thesepixel electrodes. Electric charges going into and out of the pixelelectrodes are controlled by their respective TFTs.

Manufacture of this type of active matrix liquid crystal display needs atechnique for fabricating tens of thousands of TFTs on a glass substrateor quartz substrate that is at least several centimeters square.

With today's technique, it is impossible to produce a single-crystalsilicon thin film on a glass or quartz substrate that is at leastseveral centimeters square. Accordingly, generally manufactured siliconfilms are typified by films of amorphous silicon, polycrystallinesilicon, and crystallite silicon.

Where an amorphous silicon film is used, the P-channel type cannot bemade practical. Also, high-speed operation cannot be accomplished.Therefore, it is impossible to produce from TFTs using an amorphoussilicon film a peripheral driver circuit that is required to operate ator above several megahertz.

On the other hand, where a crystalline silicon film typified bypolycrystalline and crystallite silicon films is employed, the P-channelTFT can be put into practical use. Consequently, CMOS circuits can bebuilt. In addition, high-speed operations at or above several megahertzare possible. Utilizing these features, a peripheral driver circuit canbe integrated with an active matrix circuit on the same substrate.

Yet, TFTs using a crystalline silicon film suffer from reliabilityproblem and characteristic variations. These give rise to adeterioration of the quality of the displayed image.

These reliability and characteristic variation problems are caused byunstable factors contained in the processing step for creating contactholes, as well as unstable factors contained in the state of thecrystalline silicon film forming the active layer.

It is generally known that a silicon oxide film is used as an interlayerdielectric film in TFTs. However, the silicon oxide film poses problemsas described below.

The silicon oxide film shows a low etch rate during a dry etchingprocess. In order to obtain a practical etch rate, it is necessary toincrease the self-bias voltage to about 600 V. This often results inelectrostatic discharge damage due to a voltage induced acrossmultilayer metallization when conductive interconnects are formed.

Furthermore, since the etching process is carried out, using anincreased self-bias voltage, the etching process tends to be unstable.Hence, it is difficult to secure a sufficient process margin.

For example, it is difficult to taper the end portions of contact holesby devising the etching conditions.

Generally, where the active layer of TFTs is formed, using a crystallinesilicon film, it is necessary to terminate the active layer withhydrogen. That is, the dangling bonds of silicon within the crystallinesilicon film are neutralized with hydrogen, thus stabilizing theelectrical properties.

It is necessary to form an interlayer dielectric film after theformation of the active layer, irrespective of the type of TFTs.

Where a silicon oxide film is used as the interlayer dielectric film,there arises the problem that hydrogen contained in the active layer iseasily freed, because there exists only a weak bather to hydrogen withinthe silicon oxide film. This immensely contributes to instability of theTFT characteristics.

Where a silicon oxide film is used as the interlayer dielectric film, itis difficult to detect the endpoint of the etching where the etching isa dry etching process. Generally, quartz jigs are used with a holder orstage that holds a substrate.

In this case, during the dry etching process, silicon oxide constituentsare released into the etching ambient from the quartz jigs. This makesit difficult to detect the endpoint of the etching of the silicon oxidefilm.

In particular, the detection of the silicon oxide component within theambient renders it difficult to detect the endpoint of the etching ofthe silicon oxide film clearly.

This means that the number of unstable factors in the manufacturingprocess increases.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide TFTs that showstable characteristics and can be fabricated at a high yield byeliminating the difficulties with the fabrication of the TFTs.

It is another object of the invention to provide an active matrixdisplay device that shows high image quality stably and can befabricated at a high yield.

A semiconductor device disclosed herein comprises an active layerconsisting of a semiconductor, a silicon oxide film formed on the activelayer, and a multilayer silicon nitride film formed on the firstdielectric film. The silicon oxide film acts as a gate insulator film.The silicon nitride film acts as an interlayer dielectric film.

The present invention also provides a semiconductor device consisting ofTFTs comprising an active layer consisting of a crystalline silicon filmand interlayer dielectric films all of which are made of siliconnitride.

Where the silicon nitride film is used as the interlayer dielectricfilms, the following advantages can be obtained.

First, the dry etch rate is high. Also, the self-bias voltage can be setto a low value of approximately 1500 V. Consequently, etching can beeffected stably. Furthermore, a large process margin can be obtained.

Besides, there exists a high barrier against hydrogen and so release ofhydrogen contained in the active layer can be prevented. In consequence,the characteristics of the TFTs age to a lesser extent than heretofore.

In addition, the relative dielectric constant is high. Therefore,capacitors can be easily formed, using the interlayer dielectric films.Especially, in an active matrix liquid crystal display, it is necessaryto connect auxiliary capacitors to the outputs of TFTs disposed at thepixels. It is advantageous to form these auxiliary capacitors from asilicon nitride film that forms the interlayer dielectric films.

Preferably, the quality of the silicon nitride film constituting theinterlayer dielectric films in the present invention disclosed herein isso set that the internal stress lies in the range of −5×10⁹ to 5×10⁹dyn/cm².

This is important in preventing peeling of the film when a multilayerstructure is formed. Also, this is important in preventing peeling ofelectrodes and conductive interconnects formed on the interlayerdielectric films. Furthermore, this is important in preventingstress-induced breaks in contact electrodes and poor contacts.

Especially, where ITO electrodes creating pixel electrodes are formed onthe interlayer dielectric films, the above-described requirement isimportant in preventing peeling of the ITO electrodes.

These restrictions on stress become more important as the area of theactive matrix region increases. As the area of the viewing screen isincreased, the area of the active matrix region increases.

It is advantageous to design the silicon nitride films forming theinterlayer dielectric films so that the internal stresses lie in therange −5×10⁹ to 5×10⁹ dyn/cm² and that every silicon nitride film iscompressively stressed. This makes the direction of acting stressuniform for every interlayer dielectric film, which in turn is effectivein preventing peeling of the films. Also, breaks in the conductiveinterconnects and contact electrodes and poor contacts can beeffectively prevented.

Similarly, where every interlayer dielectric film is tensilely stressed,advantages arise.

Moreover, it is advantageous to suppress the variations of internalstress among the various layers of silicon nitride forming theinterlayer dielectric films to less than ±50%.

Additionally, it is advantageous to use such a silicon nitride filmforming an interlayer dielectric film that its etch rate with respect to1/10 buffered hydrofluoric acid lies in the range of 30 to 1500 Å/min.

The present invention also provides a method of fabricating asemiconductor device utilizing a silicon nitride film, the methodinvolving a step of forming the silicon nitride film by chemical vapordeposition. This method is characterized in that the internal stress ofthe silicon nitride film grown by introducing hydrogen into the filmgrowth ambient lies in the range of −5×10⁹ to 5×10⁹ dyn/cm² and that itsetch rate with respect to 1/10 buffered hydrofluoric acid lies in therange of 30 to 1500 Å/min.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1(A)-1(D) are views illustrating processing steps for fabricatingTFTs;

FIGS. 2(A)-2(D) are views illustrating processing steps for fabricatingTFTs;

FIGS. 3(A) and 3(B) are views illustrating processing steps forfabricating TFTs;

FIGS. 4(A)-4(D) are views illustrating processing steps for fabricatingTFTs;

FIGS. 5(A)-5(D) are views illustrating processing steps for fabricatingTFTs;

FIGS. 6(A)-6(B) are views illustrating processing steps for fabricatingTFTs;

FIGS. 7(A)-7(C) are views illustrating processing steps for fabricatingTFTs;

FIGS. 8(A)-8(C) are views illustrating processing steps for fabricatingTFTs; and

FIGS. 9(A)-9(D) are views illustrating processing steps for fabricatingTFTs

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1

The present invention relates to processing steps for fabricatingthin-film transistors (TFTs) arranged at pixels of an active matrixliquid crystal display.

The processing steps of the present embodiment for fabricating TFTs areshown in FIGS. 1(A)-3(B). First, as shown in FIG. 1(A), a silicon oxidefilm is formed as a buffer film 102 on a glass substrate 101 to athickness of 3000 Å by plasma CVD (chemical vapor deposition) orsputtering. The buffer film also may be made of silicon oxide.

The substrate is not limited to the glass substrate 101. A quartzsubstrate or other substrate (e.g., semiconductor substrate) on which anappropriate dielectric film is deposited also may be used. In anintegrated circuit having multilevel metallization or multilayerstructure, an appropriate insulating film can be used as the substrate.

Then, a silicon film (not shown) that will later form an active layer ofTFTs is deposited. In this embodiment, an amorphous silicon film 500 Åthick is formed by plasma CVD. The amorphous silicon film also may bebuilt up by LPCVD.

Thereafter, heat treatment and laser irradiation are carried out tocrystallize the amorphous silicon film, thus obtaining a crystallinesilicon film (not shown).

After obtaining the crystalline silicon film, it is patterned to formthe active layer 103 of the TFTs. A silicon oxide film 104 acting as agate insulator film is deposited to a thickness of 1000 Å by plasma CVD.

A silicide material or metal material for forming gate electrodes isdeposited as a film. This film is then patterned to create gateelectrodes 105 and scanning lines (also known as gate lines) 106.Although not clearly shown, it is common practice to make the gateelectrodes 105 extend from the scanning lines 106.

Silicon materials that are heavily doped and thus have decreasedresistivities can be used as the material of the gate electrodes 105 andscanning lines 106. Also, various silicide materials and metal materialstypified by aluminum and molybdenum can be employed.

In this way, a state shown in FIG. 1(A) is obtained. Under thiscondition, dopant ions are implanted to create source and drain regions.In this embodiment, phosphorus (P) ions are implanted by plasma dopingto fabricate N-channel TFTs.

After the dopant implantation, irradiation of laser light or otherintense light is effected to anneal and activate the dopant-implantedregions. This processing step may utilize a method relying on heating.

In this way, source regions 11, drain regions 13, and channel formationregions 12 are formed in a self-aligned manner.

Then, as shown in FIG. 1(B), a silicon nitride film is deposited as afirst interlayer dielectric film 107 to a thickness of 3000 Å by plasmaCVD. The thickness of this silicon nitride film can be set betweenapproximately 3000 and 5000 Å. One example of conditions under which thesilicon nitride film is grown is given in Table 1 below.

TABLE 1 Without With Item hydrogen hydrogen Film growth SiH₄ (sccm) 1010 conditions NH₃ (sccm) 75 50 N₂ (sccm) 500 50 H₂ (sccm) 0 150 Growthpressure (Torr) 0.7 0.7 RF power (W) 300 300 Set temperature (° C.) 300300 Film Growth rate (Å/min) 293 216 Characteristics In-plane uniformity±2.1 ±2.1 (%) Index of refraction 1.852 1.907 Etch rate (Å/min) 348 121Dielectric breakdown field 5.8 × 10⁶ 5.0 × 10⁶ strength (MV/cm) (J = 1.0μA/cm²) Leakage current density  5.6 × 10⁻¹⁰  3.7 × 10⁻¹⁰ (A/cm²) (E =1.0 MV/cm) Internal stress (dyn/cm²) 7.0 × 10⁹ 4.0 × 10⁹

The etch rate given in Table 1 is the value obtained when a wet etchantLAL500 produced by Hashimoto Kasei Corporation was used. The internalstress of a film can be found by varying the hydrogen content.

Table 1 shows the film growth conditions under which no hydrogen wasadded to the ambient, for comparison. The internal stress and etch ratelead us to consider that a silicon nitride film grown in an ambient towhich no hydrogen is added cannot be said to be a silicon nitride film.

The active layer 103 is hydrogen-terminated when this silicon nitridefilm is grown. That is, hydrogen mixed into the ambient and the hydrogenproduced by decomposition of ammonia are activated by the plasma energyand encroach into the crystalline silicon film forming the active layer103. This anneals the crystalline silicon film forming the active layer,so that the film is hydrogen-terminated.

As mentioned previously, a silicon nitride film presents a barrier tohydrogen. Accordingly, it can be said that the formation of the firstinterlayer dielectric film 107 acts to confine hydrogen within theactive layer 103.

Then, contact holes 108 are created in the first interlayer dielectricfilm 107 by a dry etching method (FIG. 1(C)).

The dry etching method used in this processing step is an RIE (reactiveion etching) method using mixture gas of CF₄ and O₂ as an etchant gas.

In this step, overetch can be prevented by using the silicon oxide film104 as an etch stopper.

Then, contact holes 109 extending from the silicon oxide film 104 arecreated by a wet etching method. In other words, the bottom portions ofthe contact holes 108 where the silicon oxide film 104 is exposed areetched, followed by the formation of the contact holes 109.

In this embodiment, the wet etching is effected, using an etchant thatis a mixture of hydrofluoric acid, ammonia fluoride, and a surfaceactive agent.

This removal of the silicon oxide film 104 for creating the contactholes 109 can be carried out without using any mask. In particular, theresist mask used for the formation of the contact holes 108 can be usedintact.

Alternatively, if any resist mask is not present, the contact holes 109can be formed in a self-aligned manner by making use of the contactholes 108 previously formed.

Generally, the etch rate of the silicon nitride film with respect toHF-based etchants is lower than that of the silicon oxide film by afactor of about 10 or more. Therefore, etching of the silicon oxide filmpresents little problem during the above-described step.

In this embodiment, wet etching is used in forming the contact holes109. A method relying on dry etching also may be exploited. In thiscase, the contact holes 109 may be formed subsequently to the formationof the contact holes 108. However, the etchant gas must be replaced byCHF₃ in the dry etching step (FIG. 1(D)).

After obtaining the state shown in FIG. 1(D), source interconnects 110making contact with source electrodes or source regions are fabricatedfrom an appropriate metal material (FIG. 2(A)).

Then, a silicon nitride film is formed as a second interlayer dielectricfilm 111 to a thickness of 3000 Å by plasma CVD. The thickness of thesilicon nitride film forming the second interlayer dielectric film 111may be set between 2000 and 5000 Å (FIG. 2(B)).

This second interlayer dielectric film 111 is grown under the sameconditions as the first interlayer dielectric film 107. Where the filmthickness is varied, only the conditions associated with the filmthickness are modified.

Subsequently, contact holes 112 are created in the silicon nitride filmsthat form the first interlayer dielectric film 107 and the second layerdielectric film 111, respectively (FIG. 2(C)).

This dry etching is carried out under the same conditions as theformation of the contact holes 108 shown in FIG. 1(C). However, sincethe etch depth is different, it is necessary to perform a preliminaryexperiment to determine the etching time.

Also during this step, the silicon oxide film 104 can be used as an etchstopper.

In this manner, a state shown in FIG. 2(C) results. Then, the siliconoxide film 104 exposed at the bottoms of the contact holes 112 is etchedby a wet etching method. In consequence, contact holes 113 are created.These contact holes 113 also may be formed by dry etching.

After obtaining the state shown in FIG. 2(D), an ITO film for formingpixel electrode is formed by a sputtering method, and is patterned toform the pixel electrodes 114 (FIG. 3(A)).

A final protective film 115 is formed also from a silicon nitride film(FIG. 3(B)).

An orientation film (not shown) for orienting the liquid crystalmaterial is formed on the protective film 115 and oriented.

In this way, TFTs disposed at pixel portions of an active matrix liquidcrystal display are completed.

In these TFTs, a silicon nitride film is used as an interlayerdielectric film and so contact holes can be created with highreproducibility, using a dry etching process.

Since the silicon nitride film used as the interlayer dielectric filmserves to confine hydrogen existing within the active layer, instabilityand aging of the characteristics of the TFTs can be suppressed.

Embodiment 2

The present embodiment is similar to the configuration described inEmbodiment 1 except that LDD (lightly doped drain) regions are arrangedin the TFTs. A process sequence for the present embodiment is shown inFIGS. 4(A)-4(D), 5(A)-5(D), and 6(A)-6(B). The present embodiment hasthe same process conditions and details as used in Embodiment 1.

First, a silicon oxide film 402 is formed as a buffer film on a glasssubstrate 401 to a thickness of 3000 Å. Then, an amorphous silicon film(not shown) is grown by plasma CVD. The amorphous silicon film iscrystallized by a combination of thermal processing and laser lightirradiation to obtain a crystalline silicon film (not shown).

The above-described crystalline silicon film is patterned to formislands of regions 403 (FIG. 4(A)) that will become the active layer ofTFTs later.

After building up the active layer 403, a silicon oxide film 404 actingas a gate insulator film is formed to a thickness of 1000 Å by plasmaCVD.

An aluminum film (not shown) for forming gate electrodes is formed to athickness of 4000 Å by sputtering.

This aluminum film contains 0.1% by weight of scandium to preventgeneration of hillocks and whiskers in later processing steps. Thesehillocks and whiskers are needle-like elevated portions and spikesformed by abnormal growth of aluminum in a heating step.

After growing the aluminum film (not shown), it is patterned to formgate electrodes 405. At the same time, scanning lines 406 are formed.

Then, anodization is carried out to form a porous anodic oxide film, 407and 408. This porous anodic oxide film, 407 and 408, is formed byperforming anodization within an electrolytic solution, using a cathodeof platinum and anodes consisting of aluminum film pattern portions 405and 406. In this embodiment, an aqueous solution containing 3% oxalicacid is used as the electrolytic solution.

During this anodization process, the porous anodic oxide film can begrown up to several micrometers by controlling the anodization time. Inthis embodiment, this porous anodic oxide film is grown to a thicknessof 5000 Å.

Then, anodization is again performed, using an ethylene glycol solutioncontaining a 3% tartaric acid as an electrolytic solution. As a resultof this processing step, an anodic oxide film, 409 and 410, is formed.This anodic oxide film is of the barrier type and dense in nature.

The growth distance of this dense anodic oxide film, 409 and 410, can becontrolled by the applied voltage. In this embodiment, the filmthickness is set to 700 Å. This anodic oxide film can be grown up toabout 3000 Å.

Where the thickness of this dense anodic oxide film is increased, theincreased thickness permits formation of offset gate regions. Whereeffective offset gate regions are formed, it is necessary to set thethickness of the anodic oxide film to more than 2000 Å.

Since the electrolytic solution enters the porous dense anodic oxidefilm, 409 and 410, this film is created in the state shown in FIG. 4(A).

After obtaining the state shown in FIG. 4(A), the exposed silicon oxidefilm 404 is removed. The porous anodic oxide film, 407 and 408, isremoved selectively, using a mixed acid of acetic, nitric, andphosphoric acids.

Then, dopant ions are implanted. In this embodiment, P-type ions areintroduced to form each N-channel TFT. In this processing step, a sourceregion 41, a channel formation region 42, a lightly doped (LDD) region43, and a drain region 44 are formed in a self-aligned manner (FIG.4(B)).

After the implantation of the above-described dopant ions, irradiationof laser light or other intense light is done to anneal and activate thedopant-implanted regions.

A first interlayer dielectric film 412 is formed. A silicon nitride film412 is formed as the first interlayer dielectric film 412 having athickness of 3000 Å by plasma CVD. The hydrogen content of the ambientin which the silicon nitride film is grown is so controlled that thestress in the film lies within the range of −5×10⁹ to 5×10⁹ dyn/cm².

During this processing step, the active layer 403 is simultaneouslyhydrogen-passivated.

In this way, a state shown in FIG. 4(B) is obtained. Then, contact holes413 are created by a dry etching method (FIG. 4(C)).

In this manner, a state shown in FIG. 4(C) is obtained. Contact holes414 are formed in the silicon oxide film 411 by wet etching. The contactholes also may be created by dry etching.

Thus, a state shown in FIG. 4(D) is derived. Then, source interconnects415 in contact with source electrodes 415 or source regions are formed,as shown in FIG. 5(A). In the present embodiment, these electrodes orinterconnects are made from a titanium/aluminum/titanium lamination film(FIG. 5(A)).

Then, a silicon nitride film 3000 Å thick is formed as a secondinterlayer dielectric film 416 by plasma CVD. This silicon nitride filmis grown under the same conditions as the first interlayer dielectricfilm 412 (FIG. 5(B)).

Contact holes 417 extending through the silicon nitride films 412 and416 are formed by a dry etching method (FIG. 5(C)).

Then, wet etching is carried out to form contact holes 418 reaching thedrain region 44. The contact holes 418 also may be created by a dryetching method.

In this way, the contact holes extending through the first and secondinterlayer dielectric films 412 and 416 to the drain regions 44 can beformed (FIG. 5(D)).

Thereafter, an ITO film for forming pixel electrodes is formed andpatterned to create pixel electrodes 419 as shown in FIG. 6(A).

A silicon oxide film 420 is formed as a final protective film, thusobtaining a state shown in FIG. 6(B).

In the TFTs described in the present embodiment, the lightly doped (LDD)region 43 is arranged between the channel formation region 42 and thedrain region 44 to moderate the field strength between these tworegions. This region is normally referred to as an LDD region and iseffective in lowering the OFF current.

The TFTs described in the present embodiment can have excellent abilityto hold electric charges stored in the pixel electrodes 419. Thiscapability is useful in displaying an image of higher quality.

Embodiment 3

The present embodiment relates to a structure in which a black matrix isdisposed on a TFT panel substrate. A process sequence for the presentembodiment is shown in FIGS. 7(A)-7(C). First, a silicon oxide film orsilicon nitride film is formed as a buffer film 702 on a glass substrate701.

Then, an active layer becoming a crystalline silicon film is formed. InFIG. 7(A), islands of region 703-705 form an active layer. As willbecome apparent later, regions indicated by 703, 704, and 705 become adrain region, a channel formation region, and a source region,respectively.

Subsequently, a silicon oxide film acting as a gate insulator film 706is formed. Then, gate electrodes 707 and scanning lines (gate lines) 708are formed, using a metal material or silicide material.

Under this condition, dopant ions are implanted to form the sourceregion 705, drain region 703, and channel formation region 704 in aself-aligned manner.

A silicon nitride film is formed as a first interlayer dielectric film709. Contact holes are formed in the first interlayer dielectric film709 by a dry etching method.

Then, source electrodes or source interconnects 710 are formed from anappropriate metal material. A silicon nitride film is formed as a secondinterlayer dielectric film 711.

Thereafter, a contact hole 712 reaching the drain region 703 is formedby a thy etching method. In this way, a state shown in FIG. 7(A) isobtained.

After obtaining the state shown in FIG. 7(A), a black matrix (BM)material is deposited as a film. This black matrix material can be atitanium film, chromium film, or titanium/chromium lamination film.

This black matrix material film is patterned to form a black matrix, 713and 715. At the same time, an electrode 714 in contact with the drainregion 713 is formed. That is, the electrode 714 is made from the samematerial as the black matrix (FIG. 7(B)).

After obtaining the state shown in FIG. 7(B), a silicon nitride film isformed as a third interlayer dielectric film 716 that has the same filmquality as both first interlayer dielectric film 709 and secondinterlayer dielectric film 711. This silicon nitride film has athickness of 500 Å (FIG. 7(C)).

A contact hole reaching the electrode 714 is formed. A pixel electrode717 is formed from ITO. A silicon nitride film is formed as a finalprotective film 718 (FIG. 7(C)).

In the configuration described in the present embodiment, the overlapbetween the black matrix 713 and the pixel electrode 717 form anauxiliary capacitor. The silicon nitride film has a high relativedielectric constant of about 6 to 7. Therefore, it is highlyadvantageous to use the third interlayer dielectric film 716 consistingof silicon nitride as the dielectric of a capacitor. The relativedielectric constant of the silicon oxide film is approximately 4.

Embodiment 4

The present embodiment is similar to Embodiment 3 except for thestructure by which a black matrix is arranged on the TFT substrate.First, a silicon oxide film 702 is formed as a buffer layer on a glasssubstrate 701. Then, an active layer, 703-705, is formed. Subsequently,a silicon oxide film 706 acting as a gate insulator film is deposited.

A gate electrode 707 and a scanning line 708 are formed from anappropriate metal material or silicide material. Then, a silicon nitridefilm is deposited as a first interlayer dielectric film 709. Contactholes are formed in the first interlayer dielectric film 709 by a dryetching method. In the present embodiment, contact holes are formed inthe source region 705 and in the drain region 703.

After forming the contact holes in the first dielectric film 709, asource electrode 710 and a drain electrode 800 are formed from the sameconstituent material.

Then, a silicon nitride film is deposited as a second interlayerdielectric film 711. A contact hole 801 is created in the secondinterlayer dielectric film by dry etching. During this processing step,the electrode 800 acts as an etch stopper.

In this way, a state shown in FIG. 8(A) is obtained. Then, a materialforming the black matrix is deposited as a film and patterned to formblack matrix portions 713, 715, as well as a portion 804 acting as anextractor electrode (FIG. 8(B)).

Then, a silicon nitride film is formed as a third interlayer dielectricfilm 716. A contact hole reaching the electrode 804 is created, followedby formation of pixel electrodes 717 of ITO. Then, a silicon nitridefilm 718 is formed as a final protective film (FIG. 8(C)).

Embodiment 5

The present embodiment relates to a structure in which a black matrix isarranged on a TFT substrate and pixel electrodes are in direct contactwith drain regions.

A process sequence for the present embodiment is illustrated in FIGS.9(A)-9(D). First, a silicon oxide film 902 is formed as a buffer film ona glass substrate 901. Then, an active layer, 903-905, is formed from acrystalline silicon film. Thereafter, a silicon oxide film 90 acting asa gate insulator film is deposited.

Gate electrodes 906 and scanning lines 907 are simultaneously formedfrom an appropriate metal material or silicide material. A siliconnitride film is formed as a first interlayer dielectric film 908.

After the formation of the first interlayer dielectric film 908, acontact hole for gaining access to each source region 903 is formed by adry etching method. Each source electrode 909 is formed from anappropriate metal material.

After the formation of the source electrode 909, a silicon nitride filmis deposited as a second interlayer dielectric film 910. In this way, astate shown in FIG. 9(A) is obtained.

After obtaining the state shown in FIG. 9(A), a black matrix (BM) film,911 and 912, is formed from titanium or chromium or from atitanium/chromium lamination film. In this manner, a state shown in FIG.9(B) is obtained.

After obtaining the state shown in FIG. 9(B), a silicon oxide film orsilicon nitride film is formed as a third interlayer dielectric film913. Then, contact holes 914 are formed by a dry etching method, thusresulting in a state shown in FIG. 9(C).

Then, pixel electrodes 915 are formed from ITO. A silicon nitride filmis deposited as a final protective film 916.

Also in the configuration described in the present embodiment, overlapsbetween each pixel electrode 915 and the black matrix film, 911 and 912,form is capacitors whose dielectric is formed by the interlayerdielectric film 913.

Embodiment 5

The present embodiment relates to a structure comprising: an activelayer made of a semiconductor; a silicon oxide film formed on the activelayer; and a multilayer silicon nitride film formed on the firstdielectric layer. The silicon oxide film acts as a gate insulator film.The silicon nitride film acts as an interlayer dielectric film. Themultiple layers in the interlayer dielectric film are so designed that alower layer has a higher etch rate.

A process sequence for the present embodiment is illustrated in FIGS.1(A)-1(D), 2(A)-2(D), and 3(A)-3(B). The process conditions of theprocess sequence are similar to those of Embodiment 1 unless otherwisespecified. The present embodiment is characterized in that interlayerdielectric films 107 and 111 made of silicon nitride have different etchrates.

In particular, the interlayer dielectric film 107 has a smaller etchrate, while the interlayer dielectric film 111 has a higher etch rate.

This can suppress the tendency of the diameter of each contact hole 112to increase inwardly when it is created. That is, the tendency of thehole to assume a conical shape can be suppressed.

This structure is advantageous where interlayer dielectric films areformed in multiple layers and contact holes extending through themultiple layers are needed.

The difficulties with the manufacture of TFTs can be eliminated by theuse of the invention disclosed herein. TFTs having stablecharacteristics can be obtained at a high production yield. Also, activematrix liquid crystal displays providing stable displays of high imagequality can be fabricated at a high yield.

1. A semiconductor device comprising: a substrate; a thin filmtransistor over the substrate; a first inorganic interlayer insulatingfilm over the thin film transistor; a pixel electrode over the firstinorganic interlayer insulating film and electrically connected to thethin film transistor; and a second inorganic interlayer insulating filmon and in contact with the pixel electrode.
 2. The semiconductor deviceaccording to claim 1, wherein each of the first and second inorganicinterlayer insulating films comprises silicon nitride.
 3. Thesemiconductor device according to claim 1, wherein the first and secondinorganic interlayer insulating films have internal stress acting thesame direction.
 4. The semiconductor device according to claim 3,wherein the internal stress is compressive stress.
 5. The semiconductordevice according to claim 3, wherein the internal stress is tensilestress.
 6. The semiconductor device according to claim 3, wherein avariation of the internal stress in each of the first and secondinorganic interlayer insulating films is within a range of ±50%.
 7. Thesemiconductor device according to claim 1, wherein an absolute value ofinternal stress of each of the first and second inorganic interlayerinsulating films is in 5×10⁹ dyn/cm² or less.
 8. The semiconductordevice according to claim 1, wherein the pixel electrode comprises ITO.9. A semiconductor device comprising; a substrate; a thin filmtransistor over the substrate; a first inorganic interlayer insulatingfilm over the thin film transistor; a source wiring over the firstinorganic interlayer insulating film and electrically connected to thethin film transistor; a second inorganic interlayer insulating film overthe first inorganic interlayer insulating film and the source wiring; apixel electrode over the second inorganic interlayer insulating film andelectrically connected to the thin film transistor; and a thirdinorganic interlayer insulating film on and in contact with the secondinorganic interlayer insulating film and the pixel electrode.
 10. Thesemiconductor device according to claim 9, wherein each of the firstsecond, and third inorganic interlayer insulating films comprisessilicon nitride.
 11. The semiconductor device according to claim 9,wherein the first second, and third inorganic interlayer insulatingfilms have internal stress acting the same direction.
 12. Thesemiconductor device according to claim 11, wherein the internal stressis compressive stress.
 13. The semiconductor device according to claim11, wherein the internal stress is tensile stress.
 14. The semiconductordevice according to claim 11, wherein a variation of the internal stressin each of the first, second, and third inorganic interlayer insulatingfilms is within a range of ±50%.
 15. The semiconductor device accordingto claim 9, wherein an absolute value of internal stress of each of thefirst, second, and third inorganic interlayer insulating films is in5×10⁹ dyn/cm² or less.
 16. The semiconductor device according to claim9, wherein an etching rate of the second inorganic interlayer insulatingfilm is larger than an etching rate of the first inorganic interlayerinsulating film.
 17. The semiconductor device according to claim 9,wherein the pixel electrode comprises ITO.
 18. A semiconductor devicecomprising: a substrate; a thin film transistor over the substrate; afirst inorganic interlayer insulating film over the thin filmtransistor; a source wiring over the first inorganic interlayerinsulating film and electrically connected to the thin film transistor;a second inorganic interlayer insulating film over the first inorganicinterlayer insulating film and the source wiring; a conductive layerover the second inorganic interlayer insulating film; a third inorganicinterlayer insulating film over the second inorganic interlayerinsulating film and the conductive layer; a pixel electrode over thethird inorganic interlayer insulating film and electrically connected tothe thin film transistor; and a fourth inorganic interlayer insulatingfilm on and in contact with the third inorganic interlayer insulatingfilm and the pixel electrode.
 19. A semiconductor device according toclaim 18, wherein each of the first, second, third, and fourth inorganicinterlayer insulating films comprises silicon nitride.
 20. Thesemiconductor device according to claim 18, wherein the first, second,third, and fourth inorganic interlayer insulating films have internalstress acting the same direction.
 21. The semiconductor device accordingto claim 20, wherein the internal stress is compressive stress.
 22. Thesemiconductor device according to claim 20, wherein the internal stressis tensile stress.
 23. The semiconductor device according to claim 20,wherein a variation of the internal stress in each of the first, second,third, and fourth inorganic interlayer insulating films is within arange of ±50%.
 24. The semiconductor device according to claim 18,wherein an absolute value of internal stress of each of the first,second, third, and fourth inorganic interlayer insulating films is in5×10⁹ dyn/cm² or less.
 25. The semiconductor device according to claim18, wherein an etching rate of the second inorganic interlayerinsulating film is larger than an etching rate of the first inorganicinterlayer insulating film.
 26. The semiconductor device according toclaim 18, wherein the pixel electrode comprises ITO.